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Volume 9, Issue 2
Research on EPGA Based Evolvable Hardware Chips for Solving Super-High Dimensional Equations Group

K. Li, Z. Guo, Z. Chen & B. Ge

Int. J. Numer. Anal. Mod., 9 (2012), pp. 208-216.

Published online: 2012-09

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  • Abstract

Solving a super-high dimensional equations group is widely used in science and engineering, but the slow solution speed is the biggest problem researchers face. Research on FPGA based evolvable hardware chips for solving the super-high dimensional equations group (SHDESC) is proposed in this paper. These chips can be implemented on a million-gate scale FPGA chip. The core architecture of SHDESC is a systolic array which consists of thousands of special arithmetic units and can execute many super-high dimensional matrix operations parallelly in short time as well as really achieve the purpose of high speed solution in hardware/software codesign. The experiments show that these chips can achieve high precision results in a short period of time to solve a super-high dimensional equations group.

  • Keywords

Evolvable Hardware, Super-High Dimensional Equations Group, FPGA, Hardware/Software Codesign, Systolic Array.

  • AMS Subject Headings

35R35, 49J40, 60G40

  • Copyright

COPYRIGHT: © Global Science Press

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@Article{IJNAM-9-208, author = {K. Li, Z. Guo, Z. Chen and B. Ge}, title = {Research on EPGA Based Evolvable Hardware Chips for Solving Super-High Dimensional Equations Group}, journal = {International Journal of Numerical Analysis and Modeling}, year = {2012}, volume = {9}, number = {2}, pages = {208--216}, abstract = {

Solving a super-high dimensional equations group is widely used in science and engineering, but the slow solution speed is the biggest problem researchers face. Research on FPGA based evolvable hardware chips for solving the super-high dimensional equations group (SHDESC) is proposed in this paper. These chips can be implemented on a million-gate scale FPGA chip. The core architecture of SHDESC is a systolic array which consists of thousands of special arithmetic units and can execute many super-high dimensional matrix operations parallelly in short time as well as really achieve the purpose of high speed solution in hardware/software codesign. The experiments show that these chips can achieve high precision results in a short period of time to solve a super-high dimensional equations group.

}, issn = {2617-8710}, doi = {https://doi.org/}, url = {http://global-sci.org/intro/article_detail/ijnam/621.html} }
TY - JOUR T1 - Research on EPGA Based Evolvable Hardware Chips for Solving Super-High Dimensional Equations Group AU - K. Li, Z. Guo, Z. Chen & B. Ge JO - International Journal of Numerical Analysis and Modeling VL - 2 SP - 208 EP - 216 PY - 2012 DA - 2012/09 SN - 9 DO - http://doi.org/ UR - https://global-sci.org/intro/article_detail/ijnam/621.html KW - Evolvable Hardware, Super-High Dimensional Equations Group, FPGA, Hardware/Software Codesign, Systolic Array. AB -

Solving a super-high dimensional equations group is widely used in science and engineering, but the slow solution speed is the biggest problem researchers face. Research on FPGA based evolvable hardware chips for solving the super-high dimensional equations group (SHDESC) is proposed in this paper. These chips can be implemented on a million-gate scale FPGA chip. The core architecture of SHDESC is a systolic array which consists of thousands of special arithmetic units and can execute many super-high dimensional matrix operations parallelly in short time as well as really achieve the purpose of high speed solution in hardware/software codesign. The experiments show that these chips can achieve high precision results in a short period of time to solve a super-high dimensional equations group.

K. Li, Z. Guo, Z. Chen and B. Ge. (2012). Research on EPGA Based Evolvable Hardware Chips for Solving Super-High Dimensional Equations Group. International Journal of Numerical Analysis and Modeling. 9 (2). 208-216. doi:
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