TY - JOUR
T1 - Research on EPGA Based Evolvable Hardware Chips for Solving Super-High Dimensional Equations Group
AU - K. Li, Z. Guo, Z. Chen & B. Ge
JO - International Journal of Numerical Analysis and Modeling
VL - 2
SP - 208
EP - 216
PY - 2012
DA - 2012/09
SN - 9
DO - http://doi.org/
UR - https://global-sci.org/intro/article_detail/ijnam/621.html
KW - Evolvable Hardware, Super-High Dimensional Equations Group, FPGA, Hardware/Software Codesign, Systolic Array.
AB - <p style="text-align: justify;">Solving a super-high dimensional equations group is widely used in science and engineering,
but the slow solution speed is the biggest problem researchers face. Research on FPGA
based evolvable hardware chips for solving the super-high dimensional equations group (SHDESC)
is proposed in this paper. These chips can be implemented on a million-gate scale FPGA chip. The
core architecture of SHDESC is a systolic array which consists of thousands of special arithmetic
units and can execute many super-high dimensional matrix operations parallelly in short time
as well as really achieve the purpose of high speed solution in hardware/software codesign. The
experiments show that these chips can achieve high precision results in a short period of time to
solve a super-high dimensional equations group.</p>